1. Field of the Invention
The subject invention relates generally to the field of signal processing and more particularly to circuits and methods of synchronizing digital signals.
2. Description of Related Art
In a signal processing environment, it is often necessary to transfer data between two systems having unrelated clocks. By way of example, an asynchronous system such as a state machine typically operates on outside signals which have no timing relationship to the system. In most cases, the outside signals are temporarily stored in a bistable circuit such as a flip-flop, latch or register. The bistable circuit is clocked by a strobe signal which is synchronous with the state machine but not necessarily with the outside signal.
Bistable circuits and other forms of binary storage devices have outputs which assume either one of two stable states. The outputs are either a low logic level, sometimes arbitrarily referred to as a logic "0" and a high logic level, sometimes arbitrarily referred to as a logic "1". However, bistable circuits, which usually rely on some form of internal feedback, are capable of entering an additional state, intermediate the two stable states, commonly referred to as the metastable state. Bistable circuits have the greatest probability of entering the metastable state when the input to the circuit is changing substantially at the same time the input is being stored. For example, if the bistable circuit is a clocked D type flip-flop, the flip-flop may enter the metastable state should the flip-flop be clocked substantially at the same time the input is changing. When in the metastable state, the flip-flop output may assume an intermediate level, between a logic "1" and a "0". The flip-flop may also oscillate between the two stable states. Theoretically, the flip-flop may remain in the metastable state indefinitely. However, an actual flip-flop will eventually leave the metastable state and assume a stable state, either a logic "1" or "0".
Circuits have been utilized to minimize the effects of metastability in binary storage devices, since such effects are likely to produce system errors. One such circuit, depicted in FIG. 1, functions to transfer an input signal to an asynchronous state machine (not depicted).
The state machine periodically samples various data input from an external source and responds to such inputs in a predetermined manner. The inputs are asynchronous with the state machine. The synchronizing circuit includes a pair of cascaded D-type flip-flops 10 and 12, the first of which receives one of the external input signals. Flip-flop 10 is clocked by a clock signal labeled Exit State which is provided by the state machine.
The Exit State signal, which is asynchronous with respect to the input signal, is produced when the state machine has completed the processing of the last set of input data and is ready to process additional input data.
The input signal is transferred to the Q output of flip-flop 10 upon the occurrence of the Exit State signal. The Q output will hold or store the signal until a subsequent Exit State signal is produced. In the event the input signal changes states at substantially the same time the Exit Signal is produced, there is an increased probability that flip-flop 10 will enter a metastable state.
The FIG. 1 circuit includes a fixed delay circuit 14 which delays the Exit State signal a predetermined period of time. The delay duration is selected to exceed the maximum period in which flip-flop 10 is likely to remain in a metastable state. The period is a function of the fabrication technology of flip-flop 10 as well as the circuit design of the flip-flop, with a typical maximum period being on the order of 25 to 100 nanoseconds.
The output of delay circuit 14 is used to clock the second flip-flop 12. Delay circuit 14 prevents flip-flop 12 from being clocked until flip-flop 10 has had sufficient time to exit a metastable state. The output of circuit 14 is also used as a Set Next State signal to be used by the state machine for sampling the output of flip-flop 12, such output being identical to the input signal at the time the Exit State signal was produced.
Although the FIG. 1 circuit will greatly reduce the likelihood of producing an error due to metastability of flip-flop 10, the circuit possesses at least one serious shortcoming. Flip-flop 10 is not likely to become metastable for the vast majority of input signals. However, delay circuit 14 will always produce a fixed delay, whether such delay is required or not. Thus, the speed at which the state machine can receive and process new data is significantly reduced.
The present invention overcomes the above-noted limitations of prior art synchronization circuits. Asynchronous signals can be sampled with minimum delay while maintaining a very low probability of system error. These and other advantages of the present invention will become apparent to those skilled in the art upon a reading of the following Description of the Preferred Embodiments together with the drawings.